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Ordering number : EN5686 Monolithic Digital IC LB1821M Power Brushless Motor Pre-Driver IC for OA Equipment Overview The LB1821M is a pre-driver IC that supports direct PWM drive and is appropriate for the power brushless motors used in office automation equipment. A motor drive circuit with the desired output capability (voltage and current characteristics) can be constructed by attaching a driver array at the IC output. The LB1821M includes on chip a speed control circuit that allows the motor speed to be varied using an external clock. Package Dimensions unit: mm 3148-QFP44MA [LB1821M] Features * * * * * * * Direct PWM drive output Speed discriminator + PLL speed control circuit FG and integrating amplifiers Forward/reverse switching circuit Braking circuit (short braking) Speed lock detection output Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown protection circuits. SANYO: QIP44MA Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Maximum input current Output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IREG max IO max Pd max Topr Tstg VREG pin UL, UV, and WL outputs Conditions Ratings 9 10 30 0.9 -20 to +80 -55 to +150 Unit V mA mA W C C Allowable Operating Ranges at Ta = 25C Parameter Supply voltage Input current range FG Schmitt output applied voltage FG Schmitt output current Lock detection output current Symbol VCC IREG VFGS IFGS ILD VREG pin (7 V) Conditions Ratings 4.4 to 7.0 1 to 5 0 to 8 0 to 5 0 to 20 Unit V mA V mA mA SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63097HA(OT) No. 5686-1/16 LB1821M Allowable power dissipation, Pdmax - W Ambient temperature, Ta - C Electrical Characteristics at Ta = 25C, VCC = 6.3 V Parameter Symbol ICC1 Current drain ICC2 ICC3 ICC4 Output saturation voltage Output current Output leakage current Output off voltage [Hall Amplifier] Input bias current Common-mode input voltage range Hall input sensitivity Hysteresis Input voltage low high Input voltage high low [RC Oscillator] Output high-level voltage VOH(CR)1 VOH(CR)2 VCC = 5 V VOL(CR)1 VOL(CR)2 f (CR) V(CR)1 V(CR)2 VOH(RK)1 VOH(RK)2 VOL(RK)1 VOL(RK)2 ICHG1 ICHG2 f (RK) V(RK)1 V(RK)2 VCC = 5 V C = 0.068 F 2.2 1.7 VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V R = 75 k, C = 1500 pF 1.4 1.1 3.1 2.4 1.5 1.1 3.4 2.7 1.8 1.4 19 1.6 1.3 1.8 1.5 3.7 3.0 2.1 1.7 V V V V kHz Vp-p Vp-p IHB(HA) VICM VIN(HA) VIN(HA) VSLH VSHL -4 1.5 60 17 8 -30 32 16 -16 60 30 -8 -1 VCC - 1.5 A V mVp-p mV mV mV VO (sat) IO IO leak VO off In stop mode VCC = 5 V VCC = 5 V, In stop mode UL, VL, WL output, IO = 20 mA UH, VH, WH output, VOUT = 1.4 V UL, VL, WL output UH, Vh, WH output -20 Conditions Ratings min typ 42 10 38 8 0.2 -16 max 60 20 55 18 0.7 -12 100 0.5 Unit mA mA mA mA V mA A V Output low-level voltage Oscillator frequency Amplitude [CROCK Oscillator] 3.2 2.5 0.8 0.6 -17 9 3.5 2.8 1.1 0.9 -13 13 35 2.4 1.9 3.8 3.1 1.4 1.2 -9 17 V V V V A A Hz Output high-level voltage Output low-level voltage External capacitor charge current External capacitor discharge current Oscillator frequency Amplitude 2.6 2.1 Vp-p Vp-p Continued on next page. No. 5686-2/16 LB1821M Continued from preceding page. Parameter [VCO Oscillator] Pin C output high-level voltage VOH(C)1 VOH(C)2 VOL(C)1 VOL(C)2 f (C) V(C) VRF TSD TSD VREG VIO(FG) IB(FG) VOH(FG) VOL(FG) Gain: 100x 3 100 180 250 16 f (FG) = 2 kHz VO(FGS) IL(FGS) VOH(D) VOL(D) VOH(P)1 VOH(P)2 VOL(P)1 VOL(P)2 VOH(VCO) VOL(VCO) VOL(LD) IL(LD) ILD = 10 mA VO = VCC -6.25 VCC = 5 V VCC = 5 V 4.05 3.25 1.85 1.25 IO(FGS) = 2 mA VO = VCC VCC - 1.0 VCC - 0.7 0.4 1.1 45 51 Design target value Design target value 6.6 0.2 0.4 VCC = 5 V VCC = 5 V 4.1 3.2 3.6 2.8 4.3 3.4 3.9 3.0 4.6 3.6 4.1 3.2 1.0 0.6 V V V V MHz Vp-p Symbol Conditions Ratings min typ max Unit Pin C output low-level voltage Oscillator frequency Amplitude [Current Limiter Operation] Limiter [Thermal Shutdown Operation] Thermal shutdown operating temperature Hysteresis VREG pin voltage [FG Amplifier] Input offset voltage Input bias current Output high-level voltage Output low-level voltage FG input sensitivity Schmitt amplitude for the next stage Operating frequency range Open-loop gain [FGS Output] Output saturation voltage Output leakage current [Speed Discriminator Output] Output high-level voltage Output low-level voltage [Speed Control PLL Output] 0.47 0.52 0.57 V 150 180 30 7.0 7.3 C C V -10 -1 VCC - 1.5 VCC - 1 1 +10 +1 mV A V 1.5 V mV mV kHz dB 0.1 0.5 10 V A V V 4.35 3.55 2.15 1.55 4.65 3.83 2.45 1.85 V V V V Output high-level voltage Output low-level voltage [VCO PLL Output] Output high-level voltage Output low-level voltage [Lock Detection] Output saturation voltage Output leakage current Lock range [Integrator] Input offset voltage Input bias current Output high-level voltage Output low-level voltage Open-loop gain Input bias current Gain-bandwidth product Reference voltage [Filter Amplifier] Input bias current Output high-level voltage Output low-level voltage Reference voltage 5.3 5.6 0.4 11 V V 0.1 0.5 10 +6.25 V A % VIO(INT) IB(INT) VOH(INT) VOL(INT) -10 -0.4 VCC - 1.2 60 1.6 VCC - 0.8 0.8 10 +0.4 mV A V 1.2 V dB MHz VB(INT) IB(FIL) VOH(FIL) VOL(FIL) VB(FIL)1 VB(FIL)2 VCC = 5 V -5% VCC/2 5% V -0.4 VCC - 1.2 -5% 1.5 VCC - 0.8 0.8 2.0 1.6 +0.4 A V 1.2 5% 1.7 V V V Continued on next page. No. 5686-3/16 LB1821M Continued from preceding page. Parameter [S/S Pin] Output high-level voltage Output low-level voltage Hysteresis Pull-up resistance [F/R Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [BR Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [CLK Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance Input frequency [N1 Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [N2 Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [Low Voltage Protection] Operating voltage Release voltage Hysteresis VSDL VSDH VSD 0.15 3.75 4.0 0.25 0.35 V V V VIH(N2) VIL(N2) VIN(N2)1 VIN(N2)2 VCC = 5 V RU(N2) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(N1) VIL(N1) VIN(N1)1 VIN(N1)2 VCC = 5 V RU(N1) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(CLK) VIL(CLK) Design target value Design target value 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(BR) VIL(BR) VIN(BR)1 VIN(BR)2 VCC = 5 V RU(BR) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(F/R) VIL(F/R) VIN(F/R)1 VIN(F/R)2 VCC = 5 V RU(F/R) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VOH(S/S) VOL(S/S) VIN(S/S)1 VIN(S/S)2 VCC = 5 V RU(S/S) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k Symbol Conditions Ratings min typ max Unit VIN(CLK)1 Design target value VIN(CLK)2 VCC = 5 V, Design target value RU(CLK) f (CLK) Speed Discriminator Counts N1 High or open High or open L L N2 High or open L High or open L Number of counts 64 256 128 512 No. 5686-4/16 LB1821M Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN-.) F/R=L Item 1 2 3 4 5 6 IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R=H IN2 H H L L L H IN3 L H H H L L Output Source VH WH WH UH UH VH Sink UL UL VL VL WL WL S/S Pin High or open L Stop Start BRK Pin High or open L Brake Released Pin Assignment No. 5686-5/16 LB1821M Sample Application Circuit No. 5686-6/16 LB1821M Internal Equivalent Circuit Block Diagram Speed control system PLL Speed discriminator VCO system PLL No. 5686-7/16 LB1821M IC Operation Description 1. Speed Control Circuit This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed discriminator and the PLL circuit output (using a charge pump technique) an error signal once every two FG periods. As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency is controlled to be the same frequency as the clock signal input to the CLK pin. This means that the motor speed can be changed by changing the clock frequency. 2. VCO Circuit The LB1821M includes an on-chip VCO circuit to generate the reference signal for the speed discriminator circuit. The reference signal frequency is determined by the following formula. fVCO = fCLK x number of counts fVCO: Reference signal frequency fCLK: Frequency of the externally input clock signal The range over which the reference signal can be varied is determined by the resistor and capacitor connected to the R pin (pin 36) and the C pin (pin 37) and by the VCO loop filter constants (the external constants connected to pins 41 and 42). (Reference Values) Supply voltage VCC = 5 V VCC = 6.3 V R (k) 4.7 4.7 C (pF) 390 820 The value of R must not be less than 2.7 k. Applications can handle a wider range of speed variations than would be possible if a fixed number of counts was used by changing the number of discriminator counts (which is related to the divisor in the VCO circuit). The number of counts can be switched between 64, 128, 256, and 512 by setting the N1 (pin 10) and N2 (pin 11) pins. 3. Output Drive Circuit To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with which the output is on. Since the (external) output switching is handled by the upper side output transistors, a Schottky diode or similar device must be connected between the output (OUT) and ground. This is because a through current will flows at the instant the upper side output transistors turn on if a diode with a short reverse recovery time is not used. A rectifying diode can be used between OUT and VCC. Transistors that have no parasitic diodes must be used for the lower side output transistors. If these transistors have parasitic diode components, then through currents will occur due to the reverse recovery time of the parasitic diodes despite the inclusion of the external Schottky diodes. 4. Current Limiter Circuit The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.52 V (typical), Rf: current detection resistor). The current limitation operation consists of reducing the output duty to suppress the current. 5. Speed Lock Range The speed lock range is 6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to the speed error to control the motor speed to be within the lock range. Caution is required, since the LD signal may go on initially at startup. (It will be low while two or three FG signal pulses are input.) 6. Notes on the PWM Frequency The PWM frequency is determined by the resistor and capacitor connected to the CR pin. fPWM 1/(0.48 x C x R) A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate No. 5686-8/16 LB1821M at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. The external resistor must not have a value under 30 k. 7. Hall Input Signals Input signals with an amplitude greater than the hysteresis (60 mV, maximum) are required for the Hall inputs. An input amplitude of 100 mV or greater is desirable, taking noise and other considerations into account. The Hall input DC voltage must be set to fall within the common-mode input voltage range specifications. 8. Forward/Reverse (F/R) Switching The F/R pin can be used to switch the motor direction. The direction can be switched with the F/R pin even if the motor is turning. The IC circuit is designed to compensate for the through currents that occur when the direction is switched. However, caution is required with respect to increases in the VCC voltage (due to motor current returning to the power system instantaneously) during direction switching. If this is a problem, try increasing the capacitance of the capacitor connected between the power supply and ground. 9. Brake Switching The LB1821M implements a short braking technique in which the upper side transistors (the external transistors) for all phases are turned on. (The lower side transistors for all phases are turned off.) This means that the output current during braking does not pass through the Rf (the current detection resistor) and therefore that the current limiter does not function. Thus caution is required. During braking, the upper side transistors operate at a 100% duty, regardless of the motor speed. The braking function can be operated and released in the start state. Thus motor start and stop control can be performed from the brake pin with the S/S pin at the low level, i.e., with the system in the start state. If the startup time is a problem, the motor can be started with a shorter startup time by using the brake pin for motor start/stop control than it can with the S/S pin. (This is because the stop state is a power saving state, and restarting from this state requires waiting the time required for the VCO circuit to stabilize.) 10. Constraint Protection Circuit The LB1821M includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side (external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CROCK pin. A time of a few seconds can be set with a capacitance of under 0.1 F. No. 5686-9/16 LB1821M Output system ground ... Ground for Rf and the output diodes Signal system ground ... Ground for the IC and the IC external components 15. VREG Pin If a motor drive system is formed from a single power supply, the VREG pin (pin 33) can be used to create the powersupply voltage (about 6.3 V) for this IC. The VREG pin is a shunt regulator and generates a voltage of about 7 volts by passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the range 1 to 7 mA. The external transistors must have current capacities of at least 80 mA (to cover the ICC + Hall bias current + output current |
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